1. Field of the Invention
The present invention generally relates to an improved data processing system and more specifically relates to parallel processor (P--P) apparatus employed within the system which operates simultaneously, synchronously, and in parallel with operation of the central processing unit (CPU).
2. Description of Prior Art
The data processing art is progressing at a fast pace. One of the main areas of improvement lies in the direction of faster operating speeds, or, conversely, less time needed by the system to perform a particular operation. Over the years there have emerged advances in technology and improved design techniques which made possible the presently available high system operating speed. The present invention is yet another step in this direction of data processing progress.
One of the breakthroughs in technology contributing to reduced system operation or cycle time can be found in the semiconductor industry and is commonly termed microstructure, minute electronic integrated circuit memories capable of storing binary information under control of a human programmer. Binary information, stored in "tables," can be tailored to represent specific mathematical functions. When other binary information is used sequentially in a microprogram, it can control operation of these tables, thus implementing a solution to a particular problem. Microstructures are referred to as ROM (read only memory) and RAM (random access memory) sometimes collectively referred to as control store, and PROM (programmable read only memory) sometimes referred to as writable control store. These control stores are constructed from semiconductor material typically MOS (metal oxide semiconductors), or bipolar.
One of the data processing design techniques which contributed to improved speed of operation lies not within the hardware realm, but lies within the software (programming) realm, and this technique is sometimes referred to as sub-routining. A data processing system normally operates under control of a main program, a set of instructions stored as binary information in main memory and sequentially followed by the apparatus of the system until the solution is obtained. A sub-routine is a portion of that program, a predetermined set of instructions which can be called upon at pre-selected points in the main program. The sub-routine contributes a specific set of predetermined instructions to solve a predetermined task in a highly efficient manner each time it is called upon (or accessed), whereafter the main program continues to run. Use of highly efficient sub-routines to solve specific tasks provides more efficient programming, whereby the solution is derived faster, providing a higher speed of operation.
It is thus a challenge and problem continually confronting those contributing to this art, to generate new means for processing binary data more quickly than before. Applicant provides a novel solution to this problem with the present invention.
In a sense, the present invention relates to utilization of the technology advance of microstructure hardware to solve a particular problem in the hardware realm in a highly efficient manner, the problem otherwise lending itself to solution by employment of sub-routines in the software realm. However, the additional advantage of permitting CPU-microcode-controlled operation of the present invention with simultaneous operation of the CPU, permits even additional speed of operation to be obtained when compared with the software realm, since the main program must be halted during a sub-routining operation.